A 65-nm duty-cycle corrector achieving 10% to 90% duty-correction range with < 0.86% duty-cycle error

초록

This brief introduces a dual -loop analog duty -cycle corrector (DCC) designed to enhance the in -band phase noise performance of phase -locked loops (PLLs) by achieving precise duty cycle correction over a wide input duty cycle range. The proposed DCC incorporates a duty -cycle adjustor (DCA) within each loop, working in conjunction with a low-pass filter (LPF) and a duty -control amplifier to regulate the feedback control voltage. The feedback control voltage within each loop fine-tunes the timing delay of input pulse, ensuring that the output duty cycle of each loop is adjusted to 50%. Consequently, the proposed DCC demonstrates an expanded duty correction range. The proposed DCC was fabricated in a 65-nm standard CMOS process with an active area of 0.078 mm( 2 ). Measurement results validate the efficiency of the proposed DCC in correcting a wide range of input duty cycles ( i.e., 10% to 90%) to an output duty cycle of 50% with a maximum duty cycle error of < 0 . 86% for an input clock frequency ranging from 1 MHz to 100 MHz. To further showcase its effectiveness, the duty -corrected clock was supplied to a commercially available PLL (ADF4351). This demonstrated a noteworthy reduction of approximately 19 dB in reference spurs and a 10 dBc/Hz in the in -band phase noise.

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