Parallel architecture for high-speed block cipher, HIGHT

초록

This paper presents the implementation of high-speed block, cipher, HIGHT. The proposed architecture employs parallel architecture to enhance throughput. In addition, it shares key scheduling block for encryption and decryption to reduce hardware complexity. It also introduces an efficient protocol applicable to RFID systems, implementing the HIGHT block cipher algorithm. The new HIGHT structure yields a size small enough to afford tag applications and twice as high performance with respect to conventional HIGHT implementation. The proposed protocol overcomes the security vulnerability of RFID tags, and reduces energy consumption per transaction by sharing key generation. © 2014 SERSC.

키워드