A 1 V 25 to 30 GHz three-stage linear CMOS power amplifier using driver stage RF predistortion technique

초록

This article presents a three-stage 25 to 30 GHz linear CMOS power amplifier (PA) for fifth-generation (5G) applications. In order to improve the linearity by compensating AM-AM/AM-PM distortion, we propose a driver stage RF predistortion technique in which a first drive amplifier (DA) operates in class C mode and a second DA operates in class A mode. By enhancing the linearity with the technique, the PA can be operated at more deep class-AB bias condition with less back-off. As a result, the efficiency of the PA at operating output power can thus be increased. The PA with the predistortion technique is designed and fabricated in bulk 65 nm 1 V CMOS process. The linear PA achieves 16.9 dBm P-sat with 34.5% power-added efficiency (PAE) and 15.9 dBm P-1dB with 32% PAE at 27 GHz. At an average power of 9.3 dBm, the PA achieves the EVM of -25 dBc and PAE of 11.4% at 27 GHz.

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