Implementation of a Tree-Type Systolic Array BCH Encoder

초록

BCH codes are one of the most widely used error correcting codes for the detection and correction of random errors in the modern digital communication systems. The conventional bit serial BCH cannot adequate with the recent high speed appliances. Therefore, parallel encoding algorithms are always a necessity. In this paper, we introduced a new systolic array type BCH parallel encoder. In order to prove the efficiency of the proposed algorithm, the throughput and the area overhead was compared with its counterparts. The proposed BCH encoder has a great flexibility in parallelization and the speed was increased by 40% than the original one. The results were implemented on synthesis and simulation on FPGA using VHDL.