A ΔΣ Frequency-to-Digital Converter Based Sub-Sampling DPLL without Extra Modules in Auxiliary Loop

초록

This paper presents a Sub-Sampling Digital Phase-Locked Loop (SS-DPLL) architecture that eliminates conventional auxiliary loops by reusing a unified ΔΣ Frequency-to-Digital Converter (ΔΣ FDC) across both Automatic Frequency Calibration (AFC) and Frequency Locked Loop (FLL) modes. By leveraging the same digital FDC for both coarse and fine frequency acquisition, the proposed design enables reliable locking without requiring additional analog components such as Multi-Modulus Dividers (MMDs) or Phase-Frequency Detectors (PFDs). The unification of AFC and FLL paths simplifies the architecture, allowing for significant area savings. Fabricated in 65nm CMOS, the prototype occupies only 0.24mm2 while achieving 0.848ps RMS jitter and consuming 11.8mW. The compact layout demonstrates the effectiveness of the proposed architecture in minimizing silicon area, making it well-suited for integration in area-constrained RF systems. © 2025 IEEE.

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