Solution-crystallized and conductivity-tailored ultrathin-body indium oxide for high-bias-stress-robust enhancement-mode transistors

초록

Oxide semiconductors have emerged as promising candidates for next-generation electronic devices due to their inherent advantages. However, achieving high stability under strong gate bias stress remains a critical challenge, especially for applications in advanced electronic systems. In this study, we propose a conductivity-tailored thermal crystallization strategy to significantly reduce the high-bias-stress-induced instability of indium oxide (InOX) thin-film transistors (TFTs). The introduction of yttrium oxide (YOX) capping layer effectively suppresses the unintended excessive free electrons induced during thermal annealing, thereby preventing the degradation of threshold voltage (VT) and on/off current ratio. As a result, the proposed crystallization approach simultaneously enables excellent initial electrical performance and enhanced bias stability. Notably, the dependence of VT shift (Delta VT) on electric field stress (ESTR), i.e., the slope of the Delta VT with respect to the ESTR, was highly decreased for high-crystalline InOX/YOX TFTs compared to the control group. The mathematical relationship between Delta VT and ESTR, along with the interpretation of the stretched exponential model parameters reflecting the physical mechanisms of device degradation, suggests that thermal crystallization suppresses the electron trapping in acceptor-like trap states in the bulk InOX. Therefore, these mechanisms contribute to the dramatic enhancement in high-electric field stability. These findings underscore the importance of microstructural engineering in oxide semiconductors for emerging applications requiring robust gate-field endurance and long-term device stability, including monolithic 3D integration, memory, and advanced display technologies.

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