Capacitor-Less Dual-Mode All-Digital LDO With ΔΣ-Modulation-Based Ripple Reduction

초록

This brief presents a capacitor-less digital low-dropout (DLDO) regulator, which has low steady-state voltage ripples (V-RIPP) and low output noise, suitable for driving analog circuits in system-on-chip devices. To reduce V-RIPP, a steady-state control based on Delta Sigma modulation and a clock multiplication technique are proposed. Thanks to the Delta Sigma operation, the proposed DLDO generates noise-shaped output voltage (V-OUT), reducing V-RIPP and improving its noise performance without using an output capacitor. The Delta Sigma-modulator-based controller is activated just during the steady state, triggered by a lock detector, which continuously tracks V-OUT and compares it to a reference V-REF. During the steady state, a cyclic time-to-pulse converter and a clock combiner generate an oversampling clock for the controller. The proposed DLDO was fabricated in a 110-nm CMOS process with an active area of 0.07 mm(2). The measurement results demonstrate that at V-OUT = 0.5 V, VDD = 0.6 V, and ILOAD = 500 mu A, the proposed DLDO achieves <1 mV of V-RIPP, 17.5 dB of power supply rejection (PSR) at 1 MHz, and -151 V(2)rms/Hz (dB) of power-spectral density at 51.2 kHz. Furthermore, the proposed DLDO achieves 99.77% of current efficiency and 0.25 mV/mA of load regulation while driving the maximum ILOAD of 40 mA.

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