A Fast-Transient Fully-Integrated Digital LDO With Current-Estimation Algorithm Based Coarse Loop

초록

In this brief, a fully-integrated output-capacitor-free (OCF) digital low-dropout regulator (DLDO) is proposed utilizing a current-estimation algorithm (CEA)-based coarse loop controller to achieve fast voltage droop (V-Droop) recovery with improved line and load regulations. The proposed CEA-based controller quickly determines the target output switch-code by estimating the current-voltage ratio of power MOSFETs, enabling fast V-Droop recovery during load current (ILOAD) transients. Complementing the CEA-based coarse loop, the proposed OCF-DLDO incorporates asynchronous and fine loops. The asynchronous loop supplies an instant dynamic current during I-LOAD transients, rapidly restoring the V-OUT, while the fine loop reduces output voltage ripples and quiescent current during steady-state of the DLDO. The proposed OCF-DLDO was fabricated in a 65-nm CMOS process with an active area of 0.075 mm2. Measurement results demonstrate that the proposed DLDO operates with an input voltage range of 0.6-1.2 V. For a load current step of 26 mA at V-DD = 0.6 V, the proposed DLDO recovers a V-Droop of 140 mV within 95 ns achieving a figure-of-merit of 3.74 ns with a peak current efficiency of 99.6 %.

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