Power Modeling Framework for an Asynchronous Processor

초록

This paper presents two power models for an asynchronous processor, A8051. The first one is a pipeline accurate model which models power consumption at each pipeline stage. The other one is a micro-architectural model which models power consumption at micro-operation level. Then, we demonstrate the feasibility of the proposed approach on an A8051 processor case study. The experimental results based on applying the proposed pipeline-accurate and micro-architectural power models on an A8051 processor demonstrate that the proposed power models have high accuracy with simulation times much faster than the conventional low-level power simulator. It also shows similar results compared to the conventional power model for a synchronous processor. Even though the simulation speeds for the proposed power models are approximately 100-900 times faster than the low-level power simulator, the differences are less than 18% and 15%, respectively. Thus, the proposed power models can give a guide for SoC designers who want to integrate the asynchronous processor for low-power SoC design.

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