A Fast Adaptive and Fine Stabilizer Based Digital LDO

초록

In this brief, a fully integrated digital low-dropout regulator (DLDO) is proposed to address the trade-offs between transient response and power efficiency in dynamic load conditions. The design features a fast-adaptive glitch-driven coarse loop controller, which rapidly adjusts PMOS switches using precisely generated pulses, minimizing transient recovery time (TREC) even during large load current (ILOAD) changes. Additionally, a fine voltage stabilizer ensures steady-state voltage stability by employing high-resolution PMOS control. The DLDO is fabricated in a 65-nm CMOS process, the proposed DLDO supports an input voltage range of 0.6 V to 1.2 V and achieves a regulated output voltage from 0.55 V to 1.15 V. Simulation results demonstrate a 264 mV voltage droop recovery within 19.11 ns for a 26 mA load step, achieving a figure-of-merit of 0.225 ns² and a peak current efficiency of 99.32%. The low quiescent current of 157 μA makes it highly suitable for power-efficient SoC applications requiring both fast transient response and precise voltage regulation.

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