All digital duty-cycle corrector for integrated phase noise improvement in phase-locked loop

초록

This paper presents an all-digital duty-cycle corrector (DCC) for integrated phase noise (IPN) improvement in phase-locked loops (PLL). The proposed DCC implies a duty cycle adjustor (DCA) that adjusts the output duty regardless of the input duty. The duty range of the proposed DCA is extended by the feedback loop code which is generated by reducing the duty-cycle error (DCE) within a feedback loop using a proposed cyclic time-to-digital converter. The test chip was fabricated in a 40-nm CMOS process, and it occupied an active area of 0.039 mm(2). The measured DCE of the proposed DCC is less than 1.16%. In addition, the measurements were performed by applying the proposed DCC along with a reference doubler to a PLL. The measurement results show an approximately 21-dB reduction in reference spurs with 7.29 dB and 0.54 degrees improvement in in-band PN and overall IPN of PLL, respectively.

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