A 10kHz-BW, 86.7dB-SNDR, 176.8dB-FoM, LNA-Embedded CT ΔΣ ADC for Closed-Loop Neural Recording

초록

This paper presents an LNA-embedded CT ΔΣ ADC for closed-loop neural recording. The frontend LNA is embedded in the loop filter of ΔΣ ADC to achieve low input-referred noise (IRN) and high tolerance to stimulation artifacts. A 25-level feedback RDAC is realized with a 12-tap tri-level FIR-DAC and helps to linearize the LNA, resulting in high linearity over a wide input range. The FIR-DAC's delay is compensated by a novel feedforward compensation scheme to maintain loop stability. The DC-coupled LNA is chopped at a low frequency (100kHz) and provides high input impedance, low offset, and low 1/f noise without suffering from chopper artifacts. Implemented in a 65nm CMOS process, the ADC achieves an IRN of 62.5nV/√Hz, 86.7dB SNDR, 87.5dB DR, and 97.9dB SFDR, while consuming only 11.8μ W in a 10kHz bandwidth. This corresponds to the state-of-the-art FoM of 176.8dB. © 2025 JSAP.