A 1.9-GHz silicon-on-insulator CMOS stacked-FET power amplifier with uniformly distributed voltage stresses

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초록

A 1.9-GHz single-stage differential stacked-FET power amplifier with uniformly distributed voltage stresses was implemented using 0.32-m 2.8-V thick-oxide MOSFETs in a 0.18-m silicon-on-insulator CMOS process. The input cross-coupled stacked-FET topology was proposed to evenly distribute the voltage stresses among the stacked transistors, alleviating the breakdown and reliability issues of the stacked-FET power amplifier in sub-micrometer CMOS technology. With a 4-V supply voltage, the proposed power amplifier with an integrated output coupled-resonator balun showed a small-signal gain of 17dB, a saturated output power of 26.1dBm, and a maximum power-added efficiency of 41.5% at the operating frequency. Copyright (c) 2017 John Wiley & Sons, Ltd.

키워드

breakdown; cascode; CMOS; cross-coupled; front-end module; power-added efficiency; saturated output power; silicon-on-insulator; stacked-FET; ENHANCEMENT; DESIGN
제목
A 1.9-GHz silicon-on-insulator CMOS stacked-FET power amplifier with uniformly distributed voltage stresses
저자
Im, Donggu; Kwon, Kuduck; Lee, In-Young
DOI
10.1002/cta.2325
발행일
2017-11
유형
Article
저널명
International Journal of Circuit Theory and Applications
권
45
호
11
페이지
1660 ~ 1672