Design of an Energy-Efficient Parity Function Circuit

초록

In this paper, we introduce an energy-efficient parity function circuit that is implemented using XOR (exclusive-OR) and XNOR (exclusive-NOR) circuits. The proposed circuit reduces the internal load capacitance on the critical path and is designed with only 8 transistors. The circuit produces perfect output signals for all input combinations. The proposed parity function circuit demonstrates a 6.4% reduction in average propagation delay time, a 29.7% decrease in power dissipation, a 36.6% decrease in power-delay product (PDP), a 43.0% decrease in energy-delay product (EDP), and a 55.6% decrease in energy-delay-delay product (EDDP), respectively. Compared with the previous circuits, the proposed circuit exhibits the improved characteristics in terms of average propagation delay time, power dissipation, PDP, EDP, and EEDP. The proposed circuits are implemented with standard CMOS 0.18um technology. Computer simulations using SPICE show that the proposed circuit performs the expected logic functions and achieves a reasonable performance. © 2023 IEEE.

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