A Fast-Transient Digital LDO With Asynchronous Coarse and Dual-Mode Fine Regulation Loops

초록

This paper presents a fully-integrated all-digital low-dropout regulator (DLDO) for efficient fine-grained power delivery and management in system-on-chip (SoC) devices. The proposed DLDO is designed to drive both digital and analog load circuits, addressing their distinct requirements. An asynchronous coarse control ensures a fast load transient response to meet the dynamic demands of digital loads. In parallel, a fine-loop voltage stabilizer, equipped with dual-mode operation, enables ripple-free and precise voltage regulation essential for noise-sensitive analog loads. The dual-mode operation employs binary-shifting to quickly reach the target output voltage (V-OUT ), followed by unary-shifting for fine-tuned V-OUT adjustment, thereby minimizing the output voltage ripples (V-RIPP ). Fabricated in a 65-nm CMOS process with an active area of 0.098 mm(2), the proposed DLDO operates with an input voltage (VDD) range of 0.6 V to 1.2 V and delivers a V-OUT of 0.55 V to 1.15 V. Worst-case measurement results demonstrate the recovery time of <= 30 ns for a 109 mV voltage droop when a (0 mA -> 25 mA) load current (I-LOAD ) is changed with an edge timing of 10 ns, achieving an overall figure-of-merit of 1.106 ns(2). The proposed DLDO achieves the worst-case V-RIPP of <= 2 mV while driving a minimum I(LOAD )of 0.5 mA.

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