Fractional-N Sampling Phase-Locked Loop with time domain sign generation using Aux-DTC and fast locking AFC

초록

An analog fractional-N sampling phase-locked loop (PLL) is presented that achieves low jitter through time-domain sign generation and rapid automatic frequency calibration (AFC). The sign bit required for DTC gain calibration is produced by an auxiliary digital-to-time converter(Aux-DTC) driven by a single accumulator, delivering finer effective resolution than conventional DAC-based methods while adding negligible circuit overhead. A binary-search AFC built around one counter steers the voltage-controlled oscillator to the target band within 1 us, after which a high-gain sampling phase detector and RC variable-slope DTC take control. Fabricated in 65 nm CMOS, the PLL operates at a 5.037 GHz carrier, consumes 39 mW from a 1.2 V supply, and measures 374 fs-rms jitter, resulting in a -232 dB figure-of-merit. © 2025 IEEE.

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